JT6N57 2002-02-13 1 toshiba cmos digital integrated circuit silicon monolithic JT6N57 lsis for serial port controller with built-in non-volatile memory JT6N57 is a low-power-dissipation, low-operating-voltage lsi developed using toshiba?s cmos and eeprom technology combined. the lsi integrates a serial i/o controller and 4-kb eeprom on a single chip. with low power dissipation, 3- to 5-v operating voltage, sleep mode, and battery level detector, JT6N57 is ideal for hand-held devices and battery-operated systems. to protect data, JT6N57 can prohibit write to eeprom when the lsi is abnormal (eg, power supply voltage is low). JT6N57 features protect bits which prevent written data from being erroneously overwritten, a response function which confirms that operation is normal, and a parity check function which confirms that data communications are performed correctly. features built-in eeprom: 4 kbytes (32 bytes/page 128 pages) pins: five (v dd , gnd, clk, rst, i/o (i/o-port-only pin)) battery level detector (anti-erroneous eeprom write operations) byte/page-write/read function sleep mode (low-power dissipation at standby for input) operating voltage: 2.7 to 5.5 v operating frequency: 1 khz to 1 mhz (1 khz to 100 khz for page-write) response function and function to display after reset information about the lsi type eeprom protect bits against erroneous overwrite parity check function package: chip/wafer note: overwrite time: 8 ms (max) number of writes: 10 5 times (provisional) year for retaining data: 10 years (provisional)
JT6N57 2002-02-13 2 block diagram pad functions pad input or output name and function i/o input or output i/o port: serial interface for external devices. internally pulled up. rst input reset: input for reset signals from external devices. schmitt trigger input with internal pull-up. clk input clock: input for clock signals from external devices. schmitt trigger input with internal pull-up. v dd power supply: input for power supply from external devices. gnd ground: input for power supply from external devices. ( 0 v) equivalent circuit diagrams (1) clk, rst both clk and rst are schmitt trigger inputs with a pull-up resistor. (2) i/o serial i/o interface with a pull-up resistor. serial i/o control system control eeprom (4 kbytes) JT6N57 i/o clk v dd gnd rst clk or rst inpu t figure 1 figure 2 i/o output latch i/o control input
JT6N57 2002-02-13 3 external view pad coordinates ( m, m) signal (x point, y point) signal (x point, y point) rst (900, 50) v dd (900, 1060) clk (900, 1030) gnd ( 880, 1050) i/o ( 880, 1040) 1. data memory features are listed below: 4 kbytes (32 bytes 128 pages) automatic byte overwrite automatic page overwrite (32 bytes) data protection function by protect bits write cycle time: 8 ms (max) figure 3 below is the memory map. gnd v dd i/o clk y x (0, 0) rst chip size l x : 2.19 mm l y : 2.88 mm pad size 100 m 100 m figure 3 memory map 0000 0020 0001 0021 001e 003e 001f 003f 0fc0 0fe0 0fc1 0fe1 0fde 0ffe 0fdf 0fff .... .... ~ .... ~ .... .... .... ~ .... ~ .... 32 bytes 128 pages pages (a11~a5) (1 bit/page) protect bit (d7) addresses within page (a4 to a0)
JT6N57 2002-02-13 4 2. write to eeprom JT6N57 supports a page write mode for 1-byte write and 32-byte (a4 to a0) write, thus implementing high-speed data storing. 3. protect bits JT6N57 supports protect bits which prohibit writes to eeprom in units of pages. a protect bit prevents data from being erroneously written to or erased from eeprom. writing to a protect bit is the same as writing to the eeprom data area. a protect bit is assigned to each page. the protect bit address uses a11 to a5 to specify the page. a4 to a0 can be any value. the data bus for input/output of a protect bit is d7. once a protect bit is set to disable write to eeprom, the protect bit cannot be modified. protect bit (d7) value write to eeprom data area 0 disable 1 enable 4. basic timing figure 4 shows the timing when JT6N57 is reset by a reset signal ( rst ). to reset JT6N57, the rst pin must be low for 3 clks or longer from a clk falling edge followed by a rising edge. after the reset signal ( rst ) goes high, information about the lsi type is output at the seventh clk rising edge following the rising edge of the next clk signal. i/o input can start from the 35 th clk. 5. sleep mode at standby for i/o input after reset or at completion of command execution, JT6N57 automatically enters low-power-dissipation state (sleep mode). JT6N57 is woken up from sleep mode by command input. 6. battery level detector prohibits erroneous write to eeprom at low power supply voltage to protect data. if power supply voltage is abnormal, the response function indicates abnormality. 7. parity check function an even-parity check function is used for data transfer. whether communication data are transmitted/received correctly is checked. if data reception is abnormal, the function prohibits command reception, indicating abnormality using the response function. 8. response function whether command transmission is normal can be checked. the response function outputs whether there is a parity error or 2-state battery level detector (bld) error. if operation is normal, outputs 00h. figure 4 timing at reset information about lsi type clk rst
JT6N57 2002-02-13 5 maximum ratings (levels are shown with gnd 0 v.) characteristics symbol rating unit supply voltage v dd 0.5~6.0 v input voltage v in 0.5~v dd 0.5 v operating temperature t opr 40~85 c storage temperature t stg 55~125 c electrical characteristics dc characteristics (unless otherwise noted, v dd 2.7~5.5 v, gnd 0 v, ta 40~85c) parameter pad symbol test condition min max unit rst v dd 0.8 v dd 0.3 v clk v dd 0.7 v dd 0.3 v high-level input voltage i/o v ih v dd 0.7 v dd 0.3 v rst 0.3 v dd 0.2 v clk 0.3 v dd 0.2 v low-level input voltage i/o v il 0.3 v dd 0.2 v high-level output voltage v oh i oh 100 a, v dd 2.5 v v dd 0.8 v dd v low-level output voltage i/o v ol i ol 1 ma, v dd 2.5 v 0 0.4 v rst v in v dd 0.8~v dd 20 10 a high-level input current clk i ih v in v dd 0.7~v dd 20 10 a rst v in gnd~v dd 0.12 50 0.1 a low-level input current clk i il v in gnd~v dd 0.12 50 0.1 a pull-up resistance i/o r in 10 30 k battery level detection voltage v dd bld 2.10 2.65 v normal conditions v dd 5.5 v, f (clk) 1 mhz 7 ma battery open check (clk in) v dd 5.5 v, f (clk) 1 mhz 70 a current dissipation sleep mode (clk h stop) v dd i dd v dd 5.5 v, f (clk) 1 mhz 7 a
JT6N57 2002-02-13 6 ac characteristics (unless otherwise noted, v dd 2.7~5.5 v, gnd 0 v, ta 40~85c) ac characteristics at byte write/read and page read (values enclosed by square brackets [ ] are ac characteristics at page write) parameter pad symbol test condition min max unit clock cycle time clk t cyc figure 5 1.0 [10] 1000 [1000] s clock pulse width (high) clk t dtyh figure 5 0.35 [3.5] tcyc 0.35 [tcyc 3.5] s clock pulse width (low) clk t dtyl figure 5 0.35 [3.5] tcyc 0.35 [tcyc 3.5] s clock fall time clk t cf figure 5 100 ns clock rise time clk t cr figure 5 100 ns i/o port fall time i/o t f figure 6 200 ns i/o port rise time i/o t r figure 6 200 ns setup time: rst fall to clk falling time rst trsf figure 7 90 ns setup time: rst rise to clk falling time rst trsr figure 7 90 ns hold time: rst rise to clk rising time rst trhd figure 7 50 ns i/o output delay to clk rising time i/o tod figure 6 200 ns hold time: i/o input rise to clk rising time i/o tihr figure 6 200 ns setup time: i/o input rise to clk rising time i/o tisr figure 6 200 ns hold time: i/o input fall to clk rising time i/o tihf figure 6 200 ns setup time: i/o input fall to clk rising time i/o tisf figure 6 200 ns eeprom write cycle time twc 8 ms eeprom data hold term ta 85c 10 years eeprom data re-write times (tentative) 10 5 times
JT6N57 2002-02-13 7 ac test conditions figure 5 clk input waveform t cyc v dd 0.7 (v dd 0.9)/2 v dd 0.2 v dd 0.7 (v dd 0.9)/2 v dd 0.2 (v dd 0.9)/2 v dd 0.2 t cr t cf t dtyh t dtyl clk figure 6 i/o input waveform v dd 0.7 v dd 0.2 v dd 0.7 v dd 0.2 t r t f i/o (input) v dd 0.7 v dd 0.2 v dd 0.7 tisf tihf v dd 0.7 v dd 0.7 v dd 0.7 tod (output) tisr v dd 0.7 v dd 0.2 tihr tod (output) clk i/o
JT6N57 2002-02-13 8 reset timing to reset JT6N57, the rst pin must be low for 3 states or longer from a clk falling edge followed by a rising edge. after the reset signal ( rst ) goes high, information about the lsi type is output at the seventh state following the rising edge of the next clk signal. i/o input can start from the 35th state. figure 7 rst input waveform clk rst v dd 0.7 trsr v dd 0.2 trsf trhd v dd 0.2 v dd 0.2 v dd 0.2 v dd 0.7 information about lsi type clk rst
JT6N57 2002-02-13 9 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ea a restrictions on product use
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